AMD Begins Production of 256-Core EPYC Venice Processor on TSMC 2nm Node

AMD announced on May 21, 2026, that its 6th-generation EPYC processor, codenamed Venice, has entered the production ramp phase on TSMC's 2nm process technology in Taiwan.

The announcement makes Venice the first high-performance computing product in the industry to reach production on the 2nm node. AMD plans to eventually expand manufacturing to TSMC's Arizona fabrication facility.

Venice is built on the Zen 6 architecture and is designed to handle AI and agentic workloads. The processor features up to 256 Zen 6 cores and is expected to deliver approximately 70% more compute performance than the current EPYC Turin lineup. Thread density is projected to improve by 30%.

The chip uses the new SP7 socket and supports 16 memory channels, providing up to 1.6 terabytes per second of bandwidth per socket. It is expected to support PCIe 6.0.

AMD held a 46% revenue share in the data center and server market as of Q1 2026. The company is counting on Venice to maintain that position as cloud providers and enterprises build denser AI and high-performance computing environments.

AMD also confirmed a follow-on processor codenamed Verano, which will also use the 2nm process. Verano is optimized for performance per dollar per watt and includes LPDDR memory support for power-constrained workloads.

The launch comes as AI infrastructure investment accelerates across the industry. Major cloud providers including Google, Amazon, Microsoft, and Meta have signaled a combined 2026 capital expenditure of approximately $725 billion, much of it directed toward data centers and custom silicon.

While the AI infrastructure story has largely focused on GPUs, AMD's Venice launch highlights that CPUs remain critical for data center orchestration, memory bandwidth, networking, and mixed workloads.