IBM Unveils 0.7-Nanometer Chip With 100 Billion Transistors Using 3D Nanostack Design

IBM has unveiled the world's first 0.7-nanometer chip technology, a development that pushes semiconductor design into new physical territory.

The chip uses a 3D "nanostack" architecture that stacks transistors vertically rather than placing them side by side on a flat surface. This approach allows IBM to pack nearly 100 billion transistors onto a chip the size of a fingernail. The design delivers either a 50 percent increase in processing power or a 70 percent reduction in energy consumption compared to current-generation chips, depending on how it is configured.

The 0.7-nanometer figure, also expressed as 7 angstroms, represents a significant step beyond the 2-nanometer chips that entered production in recent years. At this scale, individual transistors are approaching the size of a few atoms, which creates new engineering challenges around heat, electrical leakage, and manufacturing precision.

IBM said the nanostack design addresses some of these challenges by using vertical stacking to increase density without requiring transistors to be made smaller in the traditional horizontal sense.

The announcement comes as the semiconductor industry faces intense pressure to deliver more computing power for artificial intelligence workloads. Data centers running large AI models consume enormous amounts of energy, and more efficient chips could reduce both operating costs and environmental impact.

Intel is also pursuing new chip architectures, focusing on its "Crescent Island" AI inference chips that use lower-cost memory and air cooling to reduce infrastructure requirements. Micron Technology has restructured its business model around $100 billion in lifetime-value supply contracts to stabilize hardware supply for data centers and automakers.