IBM Unveils Sub-1 Nanometer Nanostack Chip Architecture, Doubling Transistor Density
IBM announced the world's first sub-1 nanometer chip technology on June 25, 2026, using a new 3D transistor design called nanostack. The architecture stacks transistors vertically to pack nearly 100 billion onto a fingernail-sized chip, roughly double the density of IBM's 2 nanometer technology. Commercial production is expected within five years.
IBM announced on June 25 that it has developed the world's first sub-1 nanometer chip technology, a milestone that could reshape the semiconductor industry and extend the life of Moore's Law for another decade.
The new architecture, called nanostack, uses a three-dimensional design that stacks transistors vertically rather than laying them flat on a silicon surface. The approach allows IBM to pack nearly 100 billion transistors onto a chip the size of a fingernail, roughly double the density of its 2 nanometer technology.
The 0.7 nanometer label, IBM clarified, is an industry benchmarking term rather than an exact physical measurement. The actual transistor features are measured in angstroms, with the new design achieving dimensions that approach the physical limits of silicon-based manufacturing.
IBM says the nanostack design delivers up to 50 percent higher performance or 70 percent greater energy efficiency compared to its 2 nanometer chips, depending on how the technology is configured. Memory density also improves significantly, with a 40 percent gain in SRAM scaling that addresses a long-standing bottleneck in chip design.
The research was conducted at IBM's facility in Albany, New York, in collaboration with ASML, Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions. IBM does not manufacture commercial chips itself but licenses its research to foundries and chip designers.
IBM said it expects commercial adoption of nanostack technology to begin within five years. The company has mapped a roadmap toward 1-angstrom features over the next decade, which would represent another significant leap in chip density.
The announcement comes as the global semiconductor industry faces intense pressure to deliver more powerful and efficient chips to support the growing demands of artificial intelligence workloads. Data centers running AI models consume enormous amounts of power, and more efficient chips could significantly reduce that energy burden.
